Senior Engineer Technology Layout

• Design and layout structures and devices for GaN discrete and IC technology development test chips
• Program parametric layout cells (Cadence Skill)
• Elaborate and implement automated design rule check
• Execute tape-out of new test chips, place mask orders and verify final data
• Document designs of test structures and devices

• A higher technical school (HTL) or university degree in Electrical Engineering, Physics or Computer Science
• 0-3 years of experience in layout (Cadence) and device design
• Good knowledge in object-oriented programming languages, e.g. C++
• Excellent English language command is a must, proficiency in German is desired
• Work flexibly across perspectives while remaining receptive to continuous feedback

We offer competitive salaries and additional benefits based on your performance, experience and qualification. The employment is in accordance with the collective salary and wage agreement for employees of the electrical and electronics industry, employment group F-G. The monthly salary is paid 14 times p.a. We offer a higher compensation depending on your expertise and skills.

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