Senior Staff Engineer Verification

Villach (Austria)

Your Role

• Create and define verification plans for digital verification of Mixed Signal designs
• Create new and improve existing verification environments in SystemVerilog language using Universal Verification Methodology (UVM) and Constrained Random approach
• Execute tests in these environments on RTL and gate-level and debug issues in design and verification environments
• Lead and coordinate other verification engineers in projects
• Closely cooperate with analog and digital designers as well as concept and other verification engineers
• Mentoring of junior colleagues, consultants and students
• Contribute to enhancement of existing methodologies and flows, by driving required innovation projects

Your Profile

• A university degree in Electrical Engineering, Computer Science, Information Technology or a similar academic discipline
• 6+ years of experience in Digital Verification. Experience with leadership responsibilities as a plus
• Excellent know-how in System Verilog, UVM, and verification tools: Xcelium, Verdi and vManager or similar
• Good knowledge of RTL design (HDL) and digital or mixed-signal circuits
• Knowledge of GIT, Python, and other programming languages as a plus

We offer competitive salaries and additional benefits based on your performance, experience and qualification. The employment is in accordance with the collective salary and wage agreement for employees of the electrical and electronics industry, employment group H (https://www.feei.at/wp-content/uploads/2024/04/minimum-wages-blue-collar-workers-2025.pdf). The monthly salary is paid 14 times p.a. We offer a higher compensation depending on your expertise and skills.

Contact: Franziska Mantei, LinkedIn

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