Senior Engineer Mixed Signal Layout

Full Custom Layout: Execute full-custom IC and block-level layout from schematic to tape-out for ADC mixed-signal components. Layout Optimization: Implement precise matching techniques and isolation strategies to prevent noise coupling in sensitive analog front-ends. Physical Verification: Run and debug full-chip physical verifications, including DRC, LVS, ERC, and antenna rule checks. Parasitic Management: Analyze and minimize parasitic resistance, capacitance, and inductance to ensure signal and power integrity. Top-Level Integration: Perform floor planning, pad-ring assembly, and final chip integration, considering ESD, latch-up, and electromigration guidelines. Leadership & Mentorship: Provide technical leadership during project execution and mentor junior layout engineers within the team.

• Bachelor's or master's degree in electrical engineering or comparable field
• 5+ years of hands-on experience in CMOS and FinFET semiconductor technologies
• High proficiency with Cadence Virtuoso, Siemens Calibre, and other EDA tools
• Excellent analytical and communication skills
• Fluent in English

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