Digital Verification Engineer

Infineon Technologies Austria AG
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KI-Zusammenfassung

Als Digital Verification Engineer sind Sie verantwortlich für die Entwicklung und Pflege umfassender Verifikationsumgebungen für Automotive MCU IPs. Sie erstellen Tests, analysieren Verifikationsmetriken und arbeiten eng mit Designingenieuren zusammen, um komplexe Probleme zu debuggen. Diese Position erfordert Kenntnisse in SystemVerilog und UVM sowie Erfahrung in der Automatisierung mit Python oder Shell-Skripten.

Digital Verification Engineer (f/m/div)

Villach (Austria)

Your Role

  • Verification Implementation: Develop and maintain comprehensive verification environments for Automotive MCU IPs using SystemVerilog and Universal Verification Methodology (UVM)
  • Test Development: Create directed tests, random constraint-based tests, and coverage-driven test plans to ensure functional correctness
  • Metrics Analysis: Monitor, analyze, and report on verification metrics (code coverage, functional coverage, and assertion coverage) to drive test closure
  • Debug & Troubleshooting: Collaborate with design engineers to debug complex issues, isolate root causes and validate fixes
  • Automation & Scripting: Utilize Python and Shell scripts to automate regression flows, manage simulation data, and streamline daily workflows within a Linux environment
  • Tool Integration: Work with industry-standard verification tools and simulators to optimize performance and efficiency
  • Team Collaboration: Contribute actively to code reviews, design reviews and agile ceremonies within a supportive team that encourages knowledge sharing and professional development

Your Profile

  • Master's degree in Electrical Engineering, Computer Engineering, Telematics, Information Technology or a related field
  • 0-2 years of professional experience in digital verification is a plus - fresh graduates with strong academic projects are encouraged to apply
  • Hands-on experience through internships or academic projects in digital design or verification is highly valued
  • Languages: Proficiency in SystemVerilog is mandatory. Solid understanding of Object-Oriented Programming (OOP) concepts
  • Methodologies: Strong knowledge of Universal Verification Methodology (UVM) components and architecture
  • Scripting: Practical experience with Python or Shell (Bash) scripting for automation and data processing
  • Operating System: Comfortable working in a Linux environment
  • Concepts: Fundamental understanding of digital logic, microcontroller architecture, and verification metrics (coverage analysis)

We are filling this position through one of our leasing partners. A valid work permit for Austria (RWR+ Card) or EU citizenship is a prerequisite for this position. This position is subject to the collective agreement for workers and employees of EEI with a minimum salary of € 4.341,85 (link). The monthly salary is paid 14 times p.a. A higher payment is negotiable depending on your expertise and skills.

Contact: Maria Pollai-Schlintl, LinkedIn

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