Senior Engineer Technology Layout

Join as Professional. Permanent employment.

Your Role

• Design and layout structures and devices for GaN discrete and IC technology development test chips
• Program parametric layout cells (Cadence Skill)
• Elaborate and implement automated design rule check
• Execute tape-out of new test chips, place mask orders and verify final data
• Document designs of test structures and devices

Your Profile

• Higher technical school or university degree in Electrical Engineering, Physics or Computer Science
• 0-3 years of experience in layout (Cadence) and device design
• Good knowledge in object-oriented programming languages, e.g. C++
• Excellent English command required; German proficiency desired
• Work flexibly across perspectives with continuous feedback

We offer competitive salaries based on performance, experience and qualification, paid 14 times annually according to the collective salary agreement for the electrical and electronics industry (group F-G).
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